1. Field of the Invention
Embodiments of the present invention generally relate to floating gate structures useful in flash memory.
2. Description of the Related Art
As logic devices continue to scale down according to Moore's Law, processing challenges develop. One such challenge arises in floating gate NAND flash memory chips, which feature transistors that incorporate two gate elements, a control gate and a floating gate, to enable each transistor to assume more than one bit value. Floating gate NAND memory forms the basis of most USB flash memory devices and memory card formats used today.
As NAND memory is scaled down, the geometry of the various components—including the physical space between the floating gates—becomes more challenging for manufacturers. To increase the space between floating gates, it is possible to slim the floating gate structures themselves. However, this approach reduces the top area of the floating gates, which leads to a dominance of sidewall capacitance of an interpoly dielectric (IPD) disposed over the floating gate. Additionally, the slimming process can be inefficient, since it requires multiple oxidation/etching iterations.
Furthermore, when reducing the thickness of the floating gate, it is possible to remove too much material, thereby producing a pointed tip on the upper surface of the floating gate. Consistent with Gauss's Law (E=Q/2*π*∈*r), which states that electric field intensity is inversely proportional to the radius of curvature, the pointed shape of the slimmed floating gate generates a strong electric field near the pointed tip of the floating gate. The strong electric field near this point results in current leakage through the IPD, which can cause device degradation and/or device failure.
With NAND flash memory increasing in popularity as a convenient storage medium, there is a need for improved manufacturing processes to overcome scaling challenges particular to NAND flash devices.